With an improvement of an integration degree of a semiconductor device in recent years, an increase in power dissipation due to a leakage current of a transistor when a circuit is not in operation has become a problem. There has been developed a semiconductor integrated circuit including a low power dissipation mode in which when the semiconductor integrated circuit is not used, power supply to the circuit (circuit block) or power supply to the entire LSI (Large Scale Integrated Circuit) is stopped to reduce a leakage current.
However, in a volatile memory such as a flip-flop, a latch, or a dynamic memory configured to store data in a capacitance thereof, stored information is lost when power is off. That is, when power supply to a semiconductor integrated circuit including the volatile memory is stopped, an internal state (stored information) of the semiconductor integrated circuit, except a nonvolatile memory, is erased. For that reason, in a semiconductor integrated circuit, it is necessary to save, in an external storage (such as a non-volatile storage equipment) or the like, data desired to be retained before the stop of the power supply.
Patent Literature 1 discloses a method and an apparatus configured to save a state of a computer system component. Patent Literature 1 discloses a configuration for providing a resume function of a battery-powered computer system after an integrated circuit in the computer system has been completely shut off. In this configuration, an internal state of the computer system is read by using a scanning latch provided in the computer system component, the internal state that has been read is stored in a save region, and then power is shut off.
In an arrangement in which a memory element is disposed separately from a circuit portion holding an internal state, as disclosed in Patent Literature 1, a time delay and power dissipation due to data transfer occur. Especially, in the case where power on/off is performed highly frequently, the time delay and the power dissipation due to the data transfer may increase.
Patent Literature 2 discloses a semiconductor device configured to be able to transition at high speed into a standby mode where power dissipation is reduced, while internal information is being held. In Patent Literature 2, before a power-off of a relevant circuit block to be brought into a standby state, or before a power-off of an entire chip, a power supply control unit activates a control signal supplied to the circuit block to cause the circuit block to save an operation result processed by the circuit block in a memory unit. When a power supply is provided again to the circuit block that has been brought into the standby state, the power supply control unit activates a control signal after start of the power supply to cause the circuit block to restore thereto the data saved in the memory unit. Flip-flops in the circuit block are configured to be connected in series, when data is saved or restored, to perform data transfer in a path different from that when a normal operation is performed. In the semiconductor device described in Patent Literature 2, there are added non-volatile memory to eliminate the need for performing a complex transfer operation, thereby making it possible to save data at high speed.
The semiconductor device described in Patent Document 2, however, has a problem that unnecessary writing and loading occurs, so that power dissipation increases. The problem arises because, each time a power supply switch provided in each module is turned on and off, data held in all volatile latches included in the module are saved to and restored from a non-volatile memory portion. The unnecessary writing and loading therefore occurs. Especially, in the case where a magnetic element is employed as a non-volatile memory, for example, a write current necessary for rewriting data is typically several 100 μA to several mA per bit, which is large. For this reason, when all non-volatile memories are rewritten for each power-off, power dissipation needed for the rewriting will increase. Further, in the computer system disclosed in each of Patent Literatures 1 and 2, it may happen that a time for saving an internal state cannot be ensured when there occurs an unexpected power supply stop due to a failure or the like.
Patent Literature 3 discloses a configuration including a non-volatile latch circuit. The non-volatile latch circuit includes a latch circuit and first and second magnetoresistive elements. When writing is performed, a current supply unit complementarily changes magnetization states of the first and second magnetoresistive elements according to a state of the latch circuit. When reading is performed, data corresponding to magnetization states of the first and second magnetoresistive elements (e.g. MTJ (Magnetic Tunnel Junction) elements) is set as data to be held by the latch circuit. Patent Literature 4 discloses a memory circuit including a bistable circuit configured to store data and ferromagnetic tunnel junction elements (MTJ1, MTJ2), each configured to store data stored in the bistable circuit according to the magnetization direction of a ferromagnetic electrode free layer in a nonvolatile manner. The memory circuit can restore the data stored in the ferromagnetic tunnel junction elements (MTJ1, MTJ2) in the nonvolatile manner to the bistable circuit.